1. Field of the Invention
The present invention relates to microprocessor architectures, and more particularly, to interrupt and exception handling in microprocessors.
2. Description of Related
In a typical microprocessor, instructions are generally executed in sequence unless a control flow varying instruction is encountered or an exception occurs. With respect to exceptions, facilities are included for changing the control flow upon the occurrence of particular events which may or may not be related to particular instructions in the instruction stream. For example, a microprocessor may include an interrupt request (IRQ) lead which, when activated by an external device, causes the microprocessor to save certain information relating to the current state of the machine, including an indication of the address of the next instruction to be executed, and then immediately transfer control to an interrupt handler which begins at some predetermined address. As another example, if an execution error such as divide-by-zero occurs during the execution of a particular instruction, the microprocessor may also save information related to the current state of the machine and transfer control to an exception handler. As yet another example, some microprocessors include a "software trap" instruction in their instruction set, which also causes the microprocessor to save information concerning the state of the machine and transfer control to an exception handler. As used herein, the terms interrupt, trap, fault and exception are used interchangeably.
In some microprocessors, an externally generated interrupt always causes the microprocessor to transfer control to the same interrupt handler entry point. If several external devices are present and able to activate the interrupt request lead, the interrupt handler must first determine which device caused the interrupt and then transfer control to a portion of code to handle that particular device. For example, the Intel 8048 microcontroller includes an INT input which, when activated, causes the microcontroller to transfer control to absolute memory location 3. The 8048 also includes a RESET input which, when activated, causes the microcontroller to transfer control to absolute memory location 0. It also includes an internal timer/counter which can generate interrupts which cause a transfer of control to absolute memory location 7.
Other microprocessors include "interrupt level" leads in addition to the interrupt request lead. For these microprocessors, when an external device activates the interrupt request lead, it also places a trap number, unique to that particular device, on the interrupt level lines. The internal hardware of the microprocessor then transfers control, or "vectors", to any of several interrupt handlers, each corresponding to a different trap number. Similarly, some microprocessors have only a single predetermined entry point for all routines written to handle internally generated exceptions, and others have facilities for vectoring automatically to a routine dependent upon a trap number defined for each particular type of internal exception that might occur.
In the past, where interrupt and exception handlers were vectored, a number of different techniques were used to determine the entry point of the appropriate handler. In one technique, a table of addresses was created, beginning at a particular table base address which was either fixed or definable by the user. Each entry in the table was the same length as the length of an address, for example two or four bytes long, and contained the entry point for a corresponding trap number. When an interrupt or exception occurred, the microprocessor first determined the base address of the table, then added m times the trap number (where m is the number of bytes in each entry), and then loaded the information stored at the resulting address into the program counter (PC) to thereby transfer control to the routine beginning at the address specified in the table entry.
In other microprocessors, an entire branch instruction was stored in each entry in the table, instead of merely the address of a handler. The number of bytes in each entry was equal to the number of bytes in a branch instruction. When an interrupt or exception was received, the microprocessor would first determine the table base address, add m times the trap number, and simply load the result into the program counter. The first instruction then executed would be the branch instruction in the table, and control would finally transfer to the appropriate exception handler.
In both of the above techniques for vectoring to a handler, a delay is encountered because a preliminary operation must be performed before the operational part of the handler can begin execution. In the first above-mentioned technique, the entry point address first had to be retrieved from the table before it could be loaded into the program counter. In the second above-described technique, an entire preliminary branch instruction had to be retrieved and executed before the substantive part of the handler could begin executing. Adder delays could be eliminated in the calculation of the table base address plus m times the trap number, by merely concatenating high-order bits from the base address with the trap number itself as lower-order bits, followed by log.sub.2 m zero bits, but the delays caused by the preliminary operations just described remained. Such delays can be detrimental in a system where the response time to handle certain types of interrupts is critical.
Another problem related to exception handling in prior art microprocessors concerns the amount of information which must be stored to be able to reinstate the "state of the machine" if and when the trap handler returns to the main instruction flow. A tradeoff exists between the desire to store as much information as possible, and the desire to minimize the delay in dispatching to a trap handler. With respect to on-chip data registers in particular, one technique that has been used is to store none of the on-chip data registers, leaving it up to the handler to temporarily store the data in each register before it can use the register for its own purposes. The handler then had to replace the data in the register before returning. The need to store and restore these registers can slow the operation of the handler significantly. In another technique, the hardware automatically stores the contents of the registers on a stack before transferring control to the handler. This technique is also inadequate since it increases hardware complexity, and also can delay transfer to the handler significantly. Thus, with the vectoring techniques described above, the delays caused by existing techniques for protecting the contents of registers when a trap handler is invoked can be unacceptable in a high performance microprocessor.